To avoid baseline wander, the same number of zeros and ones are transmitted on average. Such DC-balanced data is ensured by choosing an appropriate encoding scheme. This encoding also ensures a sufficient regularity of transitions in the encoded data pattern for downstream PLLs to acquire and maintain lock, enabling clock recovery at the receiver.
Many encoding methods specified by serial-data standards (such as 8B/10B encoding) and standard PRBS patterns produce 50% DTD on average. Therefore, DTD=0.5 is generally a good assumption. An obvious exception would be an 1010 (repeating) clock-like data pattern, for which DTD=1.